Semiconductor device and method of manufacturing the same

ABSTRACT

A semiconductor device includes a semiconductor substrate; a first insulating film formed on the top surface of the semiconductor substrate; a first gate electrode formed on the first insulating film; a second insulating film having a three-layered structure made by sequentially depositing a first kind of insulating layer, a second kind of insulating layer and a first kind of insulating layer on the first gate electrode; a second gate electrode formed on the second insulating film; a first plane including the side surface of the first gate electrode or the side surface of the second gate electrode; and a second plane including the side surface of the second kind of insulating layer, wherein distance between said first plane and said second plane does not exceed 5 nm.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2002-245727, filed on Aug. 26,2002, the entire contents of which are incorporated herein by reference.

FIELD OF THE INVENTION

This invention relates to a semiconductor device and a method ofmanufacturing the same.

BACKGROUND OF THE INVENTION

Flash memory devices have recently been brought into frequent use assemiconductor storage devices. A conventional semiconductor memorydevice having Flash memory is shown in FIGS. 14 and 15.

FIGS. 14 and 15 are enlarged cross-sectional view of a memory region ofthe conventional semiconductor device 100. The section shown in FIG. 14q corresponds to the section taken along the X-X line of FIG. 1, and thesection shown in FIG. 15 corresponds to the section taken along the Y-Yline of FIG. 1.

As shown in FIG. 14, STIS (shallow trench isolation) 40 for isolatingelement-area are formed in a semiconductor substrate 10. Anelement-forming region 45 exists between every adjacent STIs 40. On thetop surface of each element-forming region 45,a gate insulating film 20is formed, and a floating gate electrode 35 is formed on the gateinsulting film 20. The floating gate electrode 35 is made up of dopedpolysilicon layers 30, 60. The top surface and the side surfaces of thefloating gate electrode 35 are coated by an insulating film 70.Therefore, the floating gateelectrode 35 is encircled by insulatingfilms and held floating. The insulating film 70 is a so-called ONO filmmade by stacking a silicon oxide film, a silicon nitride film and asilicon oxide film. Formed on the insulting film 70 is a control gateelectrode 80. The control gate electrode 80 is made of doped silicon.Asilicide (for example, WSi) layer 90 is formed on the control gateelectrode 80. A silicon nitride film 95 is formed on the silicide layer90 and a silicon oxide film 98 is further formed on the silicon nitridefilm 95.

FIG. 15 is a cross-sectional view of the semiconductor device 100 takenalong a plane being perpendicular to the extending direction of thefloating gate electrode 35 and the control gate electrode 80 shown inFIG. 14. As shown in FIG. 15, a silicon oxide film 99 is formed on sidesurfaces of the floating gate electrode 35 and the control gateelectrode 80.

Next referring to FIGS. 17A and 17B, a method of manufacturing theconventional semiconductor device 100 is briefly explained from the stepafter formation of the silicon oxide film 98. FIGS. 17A and 17Bcorrespond to the section along the Y-Y line of FIG. 1.

As shown in FIG. 17A, after a layer such as the silicon oxide film 98 isformed by the conventional method, the silicon oxide film 98 and thesilicon nitride film 95 are patterned by photolithography and RIE(reactive ion etching). After that, using the silicon nitride film 95 asa mask, the silicide layer 90, the doped polysilicon layer (control gateelectrode) 80, the insulating film 70, the doped polysilicon layers 30,60 and the gate insulating film 20 are selectively etched by RIE.

Thereafter, the structure is annealed in an oxygen atmosphere by RTO(rapid thermal oxidation) to form the silicon oxide film 99 as shown inFIG. 17B.

FIGS. 16A and 16B show a cross-sectional structure of the semiconductordevice 100 along a boundary portion C₁ between the floating gateelectrode 35 and the control gate electrode 80. FIG. 16A shows itsaspect before the RTO processing and FIG. 16B shows its aspect after theRTO processing.

Before the RTO processing, side surfaces of the floating gate electrode35, insulating film 70 and control gate electrode 80 are flat as shownin FIG. 16A.

After the RTO processing, however, a considerable thickness of thesilicon oxide film 99 grows on side surfaces of the floating gateelectrode 35 and the control gate electrode 80, but almost no siliconoxide film grows on the side surface of the silicon nitride film 70 b.That is, the silicon oxide film 99 grows locally. As a result, thesilicon oxide film on the side surfaces of the floating gate electrode35, the control gate electrode 80 and the silicon nitride film 70 bbecomes significantly uneven in thickness. Therefore, distance d₁between the plane of the side surface of the silicon nitride film 70 band the plane of the side surfaces of the floating gate electrode 35 andthe control gate electrode 80 becomes large.

Since the distance d₂ increases after the RTO processing while thedistance d₂ is substantially zero before the RTO processing, a largemechanical stress is produced at that end of the insulating film 70 inthe boundary portion C₁, and this stress transmits to the gateinsulating film 20 through the floating gate electrode 35. In general,the gate insulating film 20 functions as a tunnel gate oxide film whenthe floating gate electrode 35 receives or deliver electric charges.Therefore, if a stress rises in the gate insulating film 20, thenelectron traps are induced at that end of the gate insulating film 20.This results in a problem such as fluctuation of the threshold voltageof the device or degradation of the electric charge mobility.

In general, as shown in FIG. 8, the greater the stress rising in thegate insulating film 20, the electron traps increase. And as shown inFIG. 10, the change of the threshold voltage increases proportionally tothe electron traps. Therefore, it is undesirable that the stress actingon the gate insulating film 20 increases.

In addition to that, as shown in FIG. 9, a change of the thresholdvoltage after repetitive write and erase (W/E) in a nonvolatilesemiconductor storage device such as flash memory is considered to occurdue to an increase of electron traps. An increase of the stress actingon the gate insulating film 20 invites an increase of electron traps inthe nonvolatile semiconductor storage device. Also from this viewpoint,it is not desirable that the stress applied to the gate insulating film20 increases.

There is a demand for a semiconductor device with lower stress acting onthe gate insulating film and lower electrons trapped in the gateinsulating film than those of conventional devices.

BRIEF SUMMARY OF THE INVENTION

A semiconductor device according to an embodiment of the inventioncomprises: a semiconductor substrate; a first insulating film formed onthe top surface of the semiconductor substrate; a first gate electrodeformed on the first insulating film; a second insulating film having athree-layered structure made.by sequentially depositing a first kind ofinsulating layer, a second kind of insulating layer and a first kind ofinsulating layer on the first gate electrode; a second gate electrodeformed on the second insulating film; a first plane including the sidesurface of the first gate electrode or the side surface of the secondgate electrode; and a second plane including the side surface of thesecond kind of insulating layer, wherein distance between said firstplane and said second plane does not exceed 5 nm.

A method of manufacturing a semiconductor device according to anembodiment of the invention comprises:

forming a first insulating film on the top surface of a semiconductorsubstrate; depositing a first gate electrode material on the firstinsulating film; forming a second insulating film having a three-layeredstructure including a first kind of insulting layer, a second kind ofinsulating layer and a first kind of insulting layer sequentiallystacked on the first gate electrode material; depositing a second gateelectrode material on the second insulating film; etching the secondgate electrode material, the second insulating film and the first gateelectrode material in a uniform pattern to form a first gate electrodemade of the first gate electrode material and to form a second electrodemade of the second gate electrode material; and oxidizing at least sidesurfaces of the fist gate electrode, side surfaces of the second gateelectrode and side surfaces of the second insulating film in an ozone(O₃) atmosphere.

A method of manufacturing a semiconductor device according to anotherembodiment of the invention comprises: forming a first insulating filmon the top surface of a semiconductor substrate; depositing a first gateelectrode material on the first insulating film; forming a secondinsulating film having a three-layered structure including a first kindof insulting layer, a second kind of insulating layer and a first kindof insulting layer sequentially stacked on the first gate electrodematerial; depositing a second gate electrode material on the secondinsulating film; etching the second gate electrode material, the secondinsulating film and the first gate electrode material in a uniformpattern to form a first gate electrode made of the first gate electrodematerial and to form a second electrode made of the second gateelectrode material; and oxidizing at least side surfaces of the firstgate electrode, side surfaces of the second gate electrode and sidesurfaces of the second insulating film in an atmosphere containinghydrogen (H₂) and oxygen (O₂).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of memory regions of a semiconductor device 200according to an embodiment of the invention;

FIG. 2 is a cross-sectional view of the semiconductor device 200 takenalong the X-X line of FIG. 1;

FIG. 3 is a cross-sectional view of the semiconductor device 200 takenalong the Y-Y line of FIG. 1;

FIG. 4A is a cross-sectional view of the semiconductor device 200, whichillustrates a manufacturing method thereof;

FIG. 4B is a cross-sectional view of the semiconductor device 200, whichillustrates a continuous portion of the manufacturing method next toFIG. 4A;

FIG. 4C is a cross-sectional view of the semiconductor device 200, whichillustrates a continuous portion of the manufacturing method next toFIG. 4B;

FIG. 4D is a cross-sectional view of the semiconductor device 200, whichillustrates a continuous portion of the manufacturing method next toFIG. 4C;

FIG. 4E is a cross-sectional view of the semiconductor device 200, whichillustrates a continuous portion of the manufacturing method next toFIG. 4D;

FIG. 4F is a cross-sectional view of the semiconductor device 200, whichillustrates a continuous portion of the manufacturing method next toFIG. 4E;.

FIG. 5A is a cross-sectional view of the semiconductor device 200, whichillustrates a manufacturing method thereof;

FIG. 5B is a cross-sectional view of the semiconductor device 200, whichillustrates a continuous portion of the manufacturing method next toFIG. 5A;

FIG. 5C is a cross-sectional view of the semiconductor device 200, whichillustrates a continuous portion of the manufacturing method next.toFIG. 5B;

FIG. 6A is an enlarged, cross-sectional view of a boundary portion C₂shown in FIG. 3 before gate oxidation;

FIG. 6B is an enlarged, cross-sectional view of the boundary portion C₂shown in FIG. 3 after gate oxidation;

FIG. 7 is a graph showing changes of quantity of electron traps withstress time;

FIG. 8 is a typical graph showing relationship between mechanical stressacting upon the gate insulating film 220 and electron traps ΔVge;

FIG. 9 is a typical graph showing relationship between W/E resistanceand threshold voltage of the memory element;

FIG. 10 is a graph showing relationship between electron traps ΔVge in aperipheral circuit element and threshold voltage changes ΔVth;

FIG. 11 is a graph showing distances d₂ and d₁ in comparison;

FIG. 12 is a graph showing relationship between the end portions C₃ , C₄and maximum electric field acting on the end portions C₃ , C₄;

FIG. 13 is a cross-sectional view of a semiconductor device 300according to the second embodiment of the invention;

FIG. 14 is an enlarged, cross-sectional view of a memory region of aconventional semiconductor device 100;

FIG. 15 is an enlarged, cross-sectional view of the memory region of aconventional semiconductor device 100;

FIG. 16A is an enlarged, cross-sectional view of a boundary portion C₁,shown in FIG. 15 before gate oxidation;

FIG. 16B is an enlarged, cross-sectional view of the boundary portionC₁, shown in FIG. 15 after gate oxidation;

FIG. 17A is a cross-sectional view of the semiconductor device 100,which illustrates a manufacturing method thereof; and

FIG. 17B is a cross-sectional view of the semiconductor device 100,which illustrates a continuous portion of the manufacturing method nextto FIG. 17A.

DETAILED DESCRIPTION OF THE INVENTION

Some embodiments of the invention will now be explained below withreference to the drawings. The embodiment, however, should not beconstrued to limit the invention.

FIG. 1 is a plan view of memory regions of a semiconductor device 200according to an embodiment of the invention. Active regions A andelement-to-element isolating regions I alternately extend in thelongitudinal direction of FIG. 1. The active regions A have formedmemory elements, and every adjacent active regions A are electricallyinsulated by an isolating region I. Gate portions G extend on the activeregions A and isolating regions I in directions across these regions Aand I.

FIG. 2 is a cross-sectional view of the semiconductor device 200 takenalong the X-X line of FIG. 1. The isolating regions I have formed STI240 whereas the active regions A have formed element-forming regions245.

The semiconductor device 200 includes a semiconductor substrate 210,gate insulating film 220 formed on the top surface of the semiconductorsubstrate 210, floating gate electrode 235 formed on the gate insulatingfilm 210, insulating film 270 formed on the top surface of the floatinggate electrode 235, control gate electrode 280 formed on the insulatingfilm 270, silicide layer 290 formed on the control gate electrode 280,silicon nitride film 295 formed on the silicide layer 290, and siliconoxide film 298 formed on the silicon nitride film 295.

The floating gate electrode 235 is insulated in a floating conditionfrom the semiconductor substrate 210 and the control gate electrode 280because of the enclosure by the gate insulating film 220, STI 240 andinsulating film 270. When a certain potential is applied to the controlgate electrode 280, an electric charge is extracted from theelement-forming region 240 by tunneling the gate insulating film 220 andcaptured by the floating gate electrode 235. Data write can be executedthereby. Holding the electric charge results in storage of data.

When a potential of the opposite polarity from that for data write isapplied to the control gate electrode 280, the electric charge isdischarged from the gate electrode 235 into the element-forming region240 by tunneling the gate insulating film 220. Data erase can beexecuted thereby.

As such, data write and erase (W/E) are carried out by tunneling of anelectric charge through the gate insulating film 220. Because of thisfunction, the gate insulating film 220 is called a tunnel gateinsulating film as well.

FIG. 3 is a cross-sectional view of the semiconductor device 200 takenalong the Y-Y line of FIG. 1. Since the Y-Y line extends across the gateportion G shown in FIG. 1, a section of a plurality of gate portions Gappears in FIG. 3. A silicon oxide film 298 is formed on side surfacesof the floating gate electrode 235 and the control gate electrode 28.The element-forming region 245 has formed a diffusion layer (not shown).

Next explained is a manufacturing method of the semiconductor device200. FIGS. 4A through 4F and FIGS. 5A through 5C are cross-sectionalviews showing the manufacturing method of the semiconductor device 200in the order of its steps. Cross-sectional views of FIGS. 4A through 4Fcorrespond to those taken along the X-X line of FIG. 1.

First referring to FIG. 4A, the top surface of the semiconductorsubstrate 210 is oxidized to form the gate insulating film 220 that isapproximately 8 nm thick. Next deposited on the gate insulating film 220are an approximately 40 nm thick doped polysilicon layer 230,approximately 90 nm thick silicon nitride film 232 and approximately 230nm thick silicon oxide film 234 by LP-CVD (low pressure chemical vapordeposition).

After that, a resist of a predetermined pattern is formed byphotolithography, and the silicon oxide film 234, silicon nitride film232, doped polysilicon layer 230, gate insulating film 220 andsemiconductor substrate 210 are selectively etched by RIE using thisresist as a mask. As a result, trenches 205 are formed in thesemiconductor substrate 210 as shown in FIG. 4A.

After that, the structure is annealed in an oxygen atmosphere by RTO(rapid thermal oxidation). Thereby, a silicon oxide film, approximately6 nm thick, is formed on the silicon side walls exposed in the trenches205.

Thereafter, a silicon oxide film 236, approximately 550 nm thick, isdeposited by HDP (high density plasma).

As shown in FIG. 4B, the silicon oxide film 236 is next polished andplanarization by CMP (chemical mechanical polishing) to expose thesilicon nitride film 232, and thereafter annealed in a nitrogenatmosphere.

As shown in FIG. 4C, the silicon oxide film 236 is next etched to adepth around 10 nm by buffered hydrofluoric acid (BHF) using the siliconnitride film 232 as a mask. Thereafter, the silicon nitride film 232 isremoved by etching using phosphoric acid. As such, the STI 240 is madeout.

Next as shown in FIG. 4D, an approximately 60 nm thick doped polysiliconlayer 260 and an approximately 130 nm thick silicon oxide film 262 aredeposited by LP-CVD. The silicon oxide film 262 is next patterned byphotolithography and RIE. Then the silicon oxide film 264 isadditionally deposited by LP-CVD to a thickness around 45 nm.

Next as shown in FIG. 4E, the entire surface of the silicon oxide film264 is etched by an etch-back technique. Thereafter, using the remaindersilicon oxide film 264 and the silicon oxide film 262 as a mask, thedoped polysilicon layer 260 is selectively etched by RIE.

After the etching of the doped polysilicon layer 260, the silicon oxidefilms 264 and 262 are removed as shown in FIG. 4F, and an insulatingfilm 270, approximately 17 nm thick, is deposited by LP-CVD. Theinsulating film 270 is a film of a three-layered structure (herein belowcalled ONO film 270) made by sequentially depositing an approximately 5nm thick silicon oxide film, approximately 7 nm thick silicon nitridefilm and approximately 5 nm thick silicon oxide film. As a result,adjacent floating gate electrodes 235 are electrically insulated fromeach other.

After the ONO film 270 is formed, approximately 80 nm thick dopedpolysilicon 280 is deposited by LP-CVD. Thereafter, an approximately 70nm thick silicide layer (such as WSi film) 290 is deposited byPVD(physical vapor deposition). Additionally, an approximately 300 nmthick silicon nitride film 295 is deposited by LP-CVD.

After that, the silicon nitride film 295 and others are processed. Thisprocess, however, does not appear in sections shown in FIGS. 4A through4F. Instead referring FIGS. 5A through 5C, that process will beexplained. Sections appearing in FIGS. 5A through 5C correspond to thosetaken along the Y-Y line of FIG. 1.

FIG. 5A illustrates a section of the element after deposition of thesilicon nitride film 295.

With reference to FIG. 5B, the silicon nitride film 295 is selectivelyetched by photolithography and RIE. Furthermore, using the siliconnitride film 295 as a mask, the silicide layer 290, doped polysilicon280, ONO film 270, doped polysilicon layers 260, 230 and silicon oxidefilm 236 are selectively etched by RIE. As a result, the gate portions Gare made out (see FIG. 1).

Next as shown in FIG. 5C, side surfaces of the silicon. nitride film295, silicide layer 290, doped polysilicon (control gate electrode) 280,ONO film 270, doped polysilicon layers 260, 230 and silicon oxide film236 are oxidized (herein below called gate oxidation as well). Gateoxidation employed here is ozone O₃ oxidation using an oxidation seedmainly containing radical oxygen. In this manner, the semiconductordevice 200 shown in FIGS. 2 and 3 is made up and manufactured.

FIGS. 6A and 6B are enlarged, crbss-sectional views of a boundaryportion C₂ between the floating gate electrode 235 and the control gateelectrode 280 shown in FIG. 3 before and after ozone (O₃) oxidation.FIG. 6Ais the cross-sectional view of the boundary portion C₂ before theozone oxidation, whereas FIG. 6B is the cross-sectional view after theozone oxidation.

Before the oxidation, side surfaces of the control gate electrode 280,floating gate electrode 235 and silicon nitride film 270 are flat asshown in FIG. 6A.

In case that dry oxidation by RTO is used in the gate oxidation processas it was in the conventional technique, side surfaces of the siliconnitride film 70 b are not oxidized (see FIG. 16B). In the instantembodiment, however, using ozone oxidation in the gate oxidationprocess, side surfaces of the silicon film 270 b in the ONO film 270 areoxidized as shown in FIG. 6B. Therefore, distance d₂ between the planeP₁ containing side surfaces of the control gate electrode 280 and thesilicon nitride film 270 b and the plane P₂ containing a correspondingside surface of the silicon nitride film 270 b of the ONO film 270 issmaller than the corresponding distance d₁ in the conventionaltechnique. As such, the instant embodiment decreases the stress appliedto the end portion of the ONO film 270.

The strong oxidation of side surfaces of the silicon nitride film 270 bin this manner contributes to preventing the end portion of the ONO film270 from thinning. It results in reducing the stress applied to the endportion of the ONO film 270 and hence reducing the stress to the gateoxide film 220.

Although this embodiment employs ozone (O₃) oxidation in the gateoxidation process, another oxidation technique of generating radicaloxygen by making hydrogen H₂ and oxygen O₂ interact under a hightemperature and a low pressure will also results in the same effect.

FIG. 7 is a typical graph that shows the constant current stress timeand the voltage Vg applied to the gate for maintaining the constantcurrent. That is, a constant current stress about 0.1 A/cm² is appliedto the gate insulating film 220 for 20 seconds. In other words, anelectric charge around 2 C/cm² is injected to the gate insulating film220.

In general, when the constant voltage stress time “t” is long, Vg oncedecreases and thereafter starts rising. Assume here that the minimumvalue of Vg is “Vmin” and Vg is “V20s” when the time t is 20 seconds.Let the electron traps ΔVge be defined by “V20s-Vmin”.

FIG. 8 is a typical graph showing relationship between mechanical stressacting upon the gate insulating film 220 and electron traps ΔVge. It isunderstood from this graph that the stress applied to the gateinsulating film 220 is proportional to the electron traps ΔVge. In thesemiconductor device 200 according to the instant embodiment, the stressapplied to the gate insulating film 220 is smaller than conventionalone, and accordingly, the electron traps ΔVge of the gate insulatingfilm 220 are less than conventional one.

FIG. 9 is a typical graph showing relationship between W/E resistanceand threshold voltage of, the memory element. It is understood from thisgraph that the write threshold voltage of the memory element varies asthe frequency of write/erase operations increase. Since thissemiconductor device 200 suffers a smaller stress acting upon the gateinsulating film 220 than conventional one, electron traps ΔVge are stillless even after repetition of write/erase operations. Therefore, theinstant embodiment can limit the threshold voltage variance ΔVth to asmaller value than conventional one.

FIG. 10 is a graph showing relationship between electron traps ΔVge in aperipheral circuit element and threshold voltage changes ΔVth. It isunderstood from this graph that electron traps ΔVge are proportional tothe threshold voltage variance ΔVth. According to this embodiment, sincethe stress applied to the gate insulating film 220 is smaller thanconventional one, electron traps ΔVge are less. Therefore, theembodiment ensures the effect of decreasing the threshold voltagevariance ΔVth in any peripheral circuit element having the gateinsulating film 220.

FIG. 11 is a graph showing the distance d₂ shown in FIG. 6B and thedistance d₁ shown in FIG. 16B in comparison. The abscissa of the graphshows thickness of an oxide film formed in each test piece (TP) insertedin the gate oxidation process. The ordinate shows distances d₁ and d₂.The distance d₂ is apparently smaller than distance d₁. That is, thestress applied to the gate insulating film in this embodiment is smallerthan the stress applied to the conventional gate insulating film 20.

In general, when the oxide film of TP is 6 nm thick or even thinner,electrons trapped in the gate insulating film 220 increase. Further, incase the thickness of the oxide film of TP is 12 nm or thicker, the needof high-temperature annealing over a relatively long time results inmaking more defects in the gate insulating film 220. Therefore,thickness of the oxide film of TP is preferably limited in the rangefrom about 6 nm to 12 nm.

The preferable range of the thickness of the oxide film of TP in therange from about 6 nm to 12 nm automatically leads to the preferablerange of the distance d₂ in the range from about 2 nm to 5 nm.

Curvature radii of end portions C₃ and C₄ of the floating gate electrode235 and the control gate electrode 280 shown in broken circles in FIG.6B are approximately 1 nm, respectively. Such large curvature radii ofthe end portions C₃ and C₄ contribute to relaxing the electric fieldconverged to the end portions of the floating gate electrode 235 and thecontrol gate electrode 280, and thereby render the ONO film 270 ishardly to break down.

FIG. 12 is a graph showing relationship between the end portions C₃, C₄and maximum electric field acting on the end portions C₃, C₄. Theelectric field increases exponentially as the curvature radiusdecreases. If the curvature radii of the floating gate electrode and thecontrol gate electrode are smaller than approximately 1 nm, an electricfield as high as approximately 20 MV/cm will be applied between the endportions of the floating gate electrode and the control gate electrode.

Because the curvature radii of the end portions C₃ and C₄ areapproximately 1 nm or more, the electric field applied to the endportions of the floating gate electrode 235 and the control gateelectrode 280 are reduced to approximately 15 MV/cm or less. As aresult, the ONO film 270 becomes hardly to break. The curvature radii ofthe end portions C₃ and C₄ are more preferably from 3 nm to 4 nmapproximately to reduce the electric field applied to the end portionsof the floating gate electrode 235 and the control gate electrode 280 toapproximately 10 MV/cm or less, thereby to render the ONO film 270 ishardly to break. Note here that FIG. 12 shows a graph in which the ONOfilm 270 is approximately 6 nm thick and the an electric field as largeas approximately 5 MV/cm is applied between the flat portion of thefloating gate electrode 235 and the flat portion of the control gateelectrode 280.

FIG. 13 is a cross-sectional view of a semiconductor device 300according to the second embodiment of the invention. The plan view ofthis embodiment appears the same as that of the first embodiment ofFIG. 1. The cross-sectional view of this embodiment appears the same asthat of the first embodiment shown in FIG. 2. The cross-sectional viewof FIG. 13 q corresponds to that taken along the Y-Y line of FIG. 1.

The semiconductor device 300 shown here is manufactured by the samemanufacturing process as that of the semiconductor device 200 from thestep shown in FIG. 4A to the step shown in FIG. 5B. After the step ofFIG. 5B, however, gate oxidation by RTO is carried out in an oxygenatmosphere. This gate oxidation is dry oxidation. The cross section ofthe semiconductor device 300 obtained thereby appears the same as thecross-sectional view of FIG. 17B when taken along the Y-Y line on theplan view of FIG. 1.

Next as shown in FIG. 13, a silicon oxide film 301 is formed by LP-CVD.This is for the purpose of preventing abnormal oxidation of the silicidelayer (WSi layer) 290 by ozone (O₃) oxidation. Thereafter, gateoxidation is carried out by using ozone oxidation using radical oxygenas the main. oxidation seed. As a result of this ozone oxidation, thesilicon oxide film 301 is annealed, and end portions of the ONO film 270are oxidized. Therefore, the boundary portion C₅ encircled by the brokencircular line exhibits the same cross-sectional view as that shown inFIG. 6B. Therefore, the semiconductor device 300 according to the secondembodiment also ensures the same effect as that of the semiconductordevice according to the first embodiment.

The silicide layer 290 may be occasionally abnormally oxidized by ozoneoxidation. However, since this embodiment forms the silicon oxide film301 by LP-CVD prior to the ozone oxidation process, the silicide layer290 is prevented from abnormal oxidization by ozone oxidation.Furthermore, according to the instant embodiment, gate oxidation carriedout by RTO in the oxygen atmosphere contributes to eliminating defectsonce produced in the gate insulating film 220 near the end portions ofthe floating gate electrode 235 and thereby to reducing electron trapsin the gate insulating film 220. Here is also the. effect of excludinghydrogen from the gate insulating film 220. Moreover, since RTO iscarried out under a higher temperature than ozone oxidation, the secondembodiment is effective for further reducing the resistance of thesilicide layer 290 than the first embodiment not using RTO.

Also when ozone oxidation used in the embodiment for gate oxidation isreplaced by another oxidizing method of generating radical oxygen inlieu of ozone (O₃) by making hydrogen (H₂) and oxygen (O₂) interactundera hightemperature and a low pressure , the same effect will beobtained.

As such, according to semiconductor device taken as one embodiment ofthe invention, the stress applied to the gate insulating film is lessthan that in the conventional device, and electrons trapped in the gateinsulating film are less than those in the conventional device.

Furthermore, according to the semiconductor device manufacturing methodtaken as one embodiment of the invention, it is possible to themanufacture a semiconductor device lower in stress applied to the gateinsulating film and less in electrons trapped in the gate insulatingfilm than the conventional device.

1-11. (Canceled)
 12. A method of manufacturing a semiconductor devicecomprising: forming a first insulating film on the top surface of asemiconductor substrate; depositing a first gate electrode material onthe first insulating film; forming a second insulating film having athree-layered structure including a first kind of insulating layer, asecond kind of insulating layer and a first kind of insulating layersequentially stacked on the first gate electrode material; depositing asecond gate electrode material on the second insulating film; etchingthe second gate electrode material, the second insulating film and thefirst gate electrode material in a uniform pattern to form a first gateelectrode made of the first gate electrode material and to form a secondelectrode made of the second gate electrode material; and oxidizing atleast side surfaces of the fist gate electrode, side surfaces of thesecond gate electrode and side surfaces of the second insulating film inan ozone (O₃) atmosphere.
 13. A method of manufacturing a semiconductordevice comprising: forming a first insulating film on the top surface ofa semiconductor substrate; depositing a first gate electrode material onthe first insulating film; forming a second insulating film having athree-layered structure including a first kind of insulating layer, asecond kind of insulating layer and a first kind of insulating layersequentially stacked on the first gate electrode material; depositing asecond gate electrode material on the second insulating film; etchingthe second gate electrode material, the second insulating film and thefirst gate electrode material in a uniform pattern to form a first gateelectrode made of the first gate electrode material and to form a secondelectrode made of the second gate electrode material; and oxidizing atleast side surfaces of the first gate electrode, side surfaces of thesecond gate electrode and side surfaces of the second insulating film inan atmosphere containing hydrogen (H₂) and oxygen (O₂).
 14. Thesemiconductor device according to claim 12 further comprising; after theetching step, carrying out dry oxidation of at least side surfaces ofthe first gate electrode, side surfaces of the second gate electrode andside surfaces of the second insulating film in an oxygen (O₂)atmosphere; and depositing an oxide film at least on side surfaces ofthe first gate electrode, side surfaces of the second gate electrode andside surfaces of the second insulating film.
 15. The semiconductordevice according to claim 13 further comprising; after the etching step,carrying out dry oxidation of at least side surfaces of the first gateelectrode, side surfaces of the second gate electrode and side surfacesof the second insulating film in an oxygen (O₂) atmosphere; anddepositing an oxide film at least on side surfaces of the first gateelectrode, side surfaces of the second gate electrode and side surfacesof the second insulating film.